The present invention relates to large-grain templates that can be used as growth surfaces for depositing semiconductor thin films. In general, the performance of electronic devices using semiconductor thin films is improved by increasing the minority carrier lifetime and/or the majority carrier lifetime. In conventional solar cells, for instance, performance is determined mostly by the minority carrier lifetime. The carrier lifetime is reduced whenever there are regions in the solar cell where minority carriers can recombine with majority carriers. This negative effect on device performance is called recombination.
In electronic devices, including solar cells, recombination occurs where the perfection of the semiconductor's crystalline lattice is disrupted. These disruptions can be a point, a line, or a surface defect, where surface defects have the most deleterious effect on carrier lifetime. Surface defects are present in all electronic devices, and include both free-surface defects on the external surface of the material, as well as defects on surfaces internal to the material, such as grain boundaries.
The highest carrier lifetimes are measured in single-crystal semiconductors, where there are no internal surfaces (grain boundaries) and very few point or line defects. In contrast, polycrystalline materials, such as those found in traditional thin film solar cells based on CdTe and CIGS, have much smaller lifetimes due to the large grain boundary surface area and high recombination at the grain boundaries.
There are two ways to reduce recombination and increase lifetime in any polycrystalline semiconductor structure. One method involves chemical treatments to passivate grain boundary surfaces and reduce their ability to support recombination. For CdTe materials, cadmium chloride (CdCl2) is commonly used to passivate grain boundaries. Although advantageous in reducing grain boundary recombination, this treatment can introduce other problems, such as majority carrier compensation and increasing point defect recombination (i.e., increasing trap states).
Another method is to increase the grain size without introducing additional point and line defects, since this has the effect of reducing the surface area available for recombination. The grain size of polycrystalline thin films produced by vapor deposition (i.e., condensation of solid films from vapors transported to a supporting growth surface or substrate, sometimes referred to as physical vapor deposition) is directly dependent on the vapor deposition conditions. For example, higher substrate temperatures and lower vapor impingement rates will increase the grain size of films deposited by physical vapor deposition. In addition, the microstructural condition of the substrate itself can impact the grain size. Substrates that introduce less strain into the growing CdTe film will result in larger CdTe grains. For instance, the largest grain CdTe thin films result from epitaxy using single-crystal substrates. If the substrate is CdTe, the process is referred to as homoepitaxy. If the substrate is not CdTe, but rather a lattice-matched and different material, the process is called heteroepitaxy. The largest grain CdTe thin films are deposited using molecular beam epitaxy (MBE) and single crystal substrates, as well as very high vacuum and low deposition rates.
Single-crystal CdTe films produced by MBE may be used as templates for homoepitaxy of CdTe, even under very high vapor impingement (e.g., deposition rate), which is present during deposition by methods such as close-spaced sublimation (CSS) and vapor transport deposition (VTD). For some applications where the substrate cost is not prohibitive, this approach greatly reduces the cost of depositing the overlying or overlayer semiconductor layer. However, the use of MBE to fabricate an intermediate template layer for the subsequent high rate deposition of CdTe (or other semiconductor materials) is likely to be cost-prohibitive for solar cell module manufacturing. Accordingly, it would be advantageous to provide a lower-cost method of fabricating a template that can be used as a growth surface for semiconductor thin films, such as CdTe.